MIM capacitors have been extensively used for semiconductor devices related to analog-to-digital conversion and digital-to-analog conversion of apparatuses employing analog signals. Conversion between analog signals and digital signals requires capacitors and resistors. Also, as signals of which bits are numerous are used to increase the amount of data processed in data signals, semiconductor devices for processing signals should provide a reliable discrimination about shapes of signals. Also, the shapes of signals should not change with such variables as voltage and temperature. If capacitors of semiconductor devices have different capacitances according to voltage or temperature, it becomes impossible to exactly determine and process signals.
However, in case of using polysilicon for capacitor electrodes, electric charges can be easily emitted through boundaries between the capacitor electrode and a dielectric layer. Dependence of polysilicon upon temperature and voltage makes a capacitance change within a significantly wide range. For this reason, capacitors of the foregoing structure are not used for semiconductor devices, which need small size and high stability. Therefore, MIM capacitors are mainly adopted for analog semiconductor devices.
Generally, formation of an MIM capacitor comprises forming a multiple layer structure of aluminum interconnections, which includes an upper interconnection, a via, and a lower interconnection, and at the same time forming lower and upper electrodes of the capacitor. FIG. 1 is a cross-sectional view of a conventional MIM capacitor and conventional aluminum interconnections. Referring to FIG. 1, an interlayer insulation layer 15 is stacked on an aluminum lower electrode 11 and an aluminum lower interconnection 13. A window, which exposes the lower electrode 11, is formed in the interlayer insulation layer 15. A dielectric layer 17 is conformally stacked on an entire surface of a semiconductor substrate, and a via contact hole is formed to expose the lower interconnection 13. An aluminum layer is then stacked on an entire surface of the semiconductor substrate and patterned to form an upper electrode 19, an upper interconnection 21, and a via contact 23.
Laborious research for copper interconnections and copper capacitor electrodes has been conducted recently in order to increase stability and discrimination about signals of semiconductor devices. This is because copper has lower resistance and higher discrimination as compared with aluminum. However, in the case of using copper for interconnections and electrodes of the MIM capacitors, the interconnections and the electrodes cannot be easily patterned through conventional photolithographic and etching processes. Accordingly, a damascene process is performed instead. A copper damascene process comprises forming a groove for an interconnection in an insulation layer, stacking copper to fill the groove, and removing the copper from the substrate excluding the groove. However, since copper may be diffused to contaminate adjacent interlayer insulation layers and induce functional problems, the copper is covered with a barrier layer. Consequently, in the case that copper is used for electrodes of the MIM capacitor, it is difficult to apply conventional processes for fabricating aluminum MIM capacitors and aluminum interconnections.
FIG. 2 is a cross-sectional view illustrating an example of an MIM capacitor with a copper electrode in a conventional semiconductor device using a copper interconnection (“A high reliability metal insulator metal capacitor for 0.18 um copper technology” by M. Armacost et al., 2000, IEEE).
Referring to FIG. 2, a capacitor 43 is formed on a semiconductor substrate 30, and the capacitor 43 is covered with lower and upper nitride layers 31 and 33. The capacitor 43 includes a base oxide layer 35, a lower electrode 37, a dielectric layer 39, and an upper electrode 41. In this case, an area of the upper electrode 41 is smaller than that of the lower electrode 37. The upper and lower electrodes 37 and 41 of the capacitor 43 are thin metal layers like TiN. An interlayer insulation layer 45 is formed on the upper nitride layer 33. A groove and a via contact hole are formed in the interlayer insulation layer 45 and filled with a barrier metal 47 and a copper layer 49. The barrier metal 47 and the copper layer 49 are polished by chemical mechanical polishing (CMP) to form interconnections. The interconnections, which are formed of the barrier metal 47 and the copper layer 49 that fill the groove and the via contact hole, are connected to the upper and lower electrodes 37 and 41, respectively, through a contact plug.
In this case, however, photolithographic process should be performed more than twice to fabricate a capacitor. Also, it grows difficult to fabricate a via contact hole due to a complicated stacked structure. In addition, an entire substrate exhibits poorer step coverage by stacking a multiple layer for the capacitor. As a result, the CMP process is required to improve the step coverage.
FIGS. 3 through 6 are cross-sectional views illustrating an example of forming an MIM capacitor and an interconnection in a semiconductor device using a copper interconnection. A lower electrode 53 and a lower interconnection 55 are formed in an insulation layer 51 formed on a substrate using a damascene process, and then an interlayer insulation layer 57 is formed. The interlayer insulation layer 57 is patterned to form a via contact hole 61 and a window 63, then a dielectric layer 59 is stacked on the resultant structure (see FIG. 3). A groove 65 for an upper interconnection is, using a photoresist pattern (not shown), formed on the interlayer insulation layer 57 (see FIG. 4). The groove 65, the via contact hole 61, and the window 63 are filled with a conductive layer to form an upper electrode 66, an intermediate interconnection 67, and a contact plug 68 (see FIG. 5). After stacking and patterning another interlayer insulation layer 71, an upper interconnection layer is stacked and patterned to form an upper contact plug 73 and an upper interconnection 72.
In the foregoing method, the interlayer insulation layer 57 and the dielectric layer 59 are selectively etched to form the groove 65. The groove 65 is formed to remove the dielectric layer 59 under the via contact hole 61, while the dielectric layer 59 still remains on the bottom of the window 63.
In this case, the via contact hole 61 should be maintained to be an appropriate depth. If the via contact hole 61 is formed too deeply, the lower interconnection may be easily attacked during an etching process for forming the via contact hole 61, and it becomes difficult to fill the via contact hole with interconnection metal due to a high aspect ratio of the via contact hole. Besides, the dielectric layer remaining on sidewalls of the via contact hole 61 lessens a width of the via contact hole 61. This makes it difficult to fill the via contact hole 61 with a conductive material. In addition, if the dielectric layer is not completely removed from bottom of the via contact hole 61, a contact resistance may be increased.